The applicants have proposed a matched filter of this kind of one in Japanese patent application number 7-212438. Paying attention that PN (Pseudo-Noise) code is a 1 bit code, a circuit for multiplication is simplified by a multiplexer.
In such an analog calculating circuit, an offset voltage is generated by a residual electrical charge in an inverter and capacitor. As a result, the accuracy of the output is comprised. In order to reduce the electrical charge, it is necessary to short-circuit the capacitance and allow, for refreshing. As it is necessary to stop the calculation when the circuit is refreshed, the calculation speed of the entire circuit is sacrificed for the sake of accuracy.
Therefore, the applicants of this invention propose the structure in Japanese patent application 7-263573 where a main sampling and holding circuit used as a sampling and holding circuit of a matched filter and a sampling and holding circuit are settled, and holding data is once held in a supplemental sampling and holding circuit when the main sampling and holding circuit is refreshed. However it is requested to reduce further the size of the circuit and consuming electric power.